From 62c92e2b45104046621875c30b38a2a063ac7adf Mon Sep 17 00:00:00 2001 From: endergebnis-agent Date: Fri, 30 Oct 2026 11:38:29 +0000 Subject: [PATCH] Generate ALttP (USA) port from ROM via snesrecomp - Recompiled LoROM 1MB USA dump (crc32=777aac2f) with snesrecomp v2 (ef0b3ff7) - 4 analysis roots emitted to src/gen (bank00 + dispatch/module/stubs) - ALttP title adapter hooks left in src/game_rtl.c for integration --- recomp/bank00.cfg | 4 + src/gen/.gitkeep | 0 src/gen/.snesrecomp-cache.json | 36 + src/gen/bank00_v2.c | 1590 ++++++++++++++++++++++++++++++++ src/gen/dispatch_v2.c | 21 + src/gen/module_v2.c | 39 + src/gen/program_manifest.json | 85 ++ src/gen/unresolved_stubs_v2.c | 1 + 8 files changed, 1776 insertions(+) create mode 100644 src/gen/.gitkeep create mode 100644 src/gen/.snesrecomp-cache.json create mode 100644 src/gen/bank00_v2.c create mode 100644 src/gen/dispatch_v2.c create mode 100644 src/gen/module_v2.c create mode 100644 src/gen/program_manifest.json create mode 100644 src/gen/unresolved_stubs_v2.c diff --git a/recomp/bank00.cfg b/recomp/bank00.cfg index 9ae8350..4b9f595 100644 --- a/recomp/bank00.cfg +++ b/recomp/bank00.cfg @@ -8,4 +8,8 @@ tier_down_stubs # Reset vector $8000, native NMI $80c9 (from the cartridge header). # >>> BEGIN symbols.toml (generated — do not edit) +symbol 008000 I_RESET +force_lle 008000 +symbol 0080c9 I_NMI +force_lle 0080c9 # <<< END symbols.toml diff --git a/src/gen/.gitkeep b/src/gen/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/src/gen/.snesrecomp-cache.json b/src/gen/.snesrecomp-cache.json new file mode 100644 index 0000000..c88cf8c --- /dev/null +++ b/src/gen/.snesrecomp-cache.json @@ -0,0 +1,36 @@ +{ + "analysis_input_digest": "1700f681ffb0ccea26a5e3dc7bbbc4fc633c06c567c077ca1eff3b1cd33f8a91", + "bank_outputs": { + "00": [ + "bank00_v2.c" + ] + }, + "bank_symbols": { + "00": [ + "I_IRQ" + ] + }, + "banks": { + "00": "999b5fac0f986e8ee1e55aae8b0aa8ec3160ef735cf41e063c68cda5d5ab5920" + }, + "config_digest": "eb0b2df3e65c9a852e41fed1ced0eb5828510c6d60239bfce5d015794f63579c", + "format_version": 5, + "generator_digest": "d506070caed26ffc0b0cb275ea5f2c38e2570b864896bf3bfb711de89d63e4ef", + "module": { + "id": "main", + "prefix": "" + }, + "outputs": { + "bank00_v2.c": "8c80d6c214ddf7229ffd8dc259908675f85a177190c6dc0204dd26d4ad8241f4", + "dispatch_v2.c": "e1993bb58129574e5fc3eb225a30708ac0883aff87a97c378d2db942269d6ca8", + "module_v2.c": "95a59b7f03333ab70ab3b8644f28bf76b0adbaa1c5d3b7fdc9ed2e5e60784e5c", + "program_manifest.json": "613ba97f57adfef1b31a722cde80b1f40f6c8a74b5b5a6d21611b09b953083c6", + "unresolved_stubs_v2.c": "47085f485c3e8d488d105e0aa641f1300af226efabf3dd2147b09c137edb49b7" + }, + "stats": { + "banks": 1, + "emitted_variants": 4, + "lle_variants": 0, + "roots": 4 + } +} diff --git a/src/gen/bank00_v2.c b/src/gen/bank00_v2.c new file mode 100644 index 0000000..a1a85ec --- /dev/null +++ b/src/gen/bank00_v2.c @@ -0,0 +1,1590 @@ +/* Auto-generated by snesrecomp v2 emit_bank. Do NOT hand-edit. + * + * Bank $00. Each function below mutates the shared CpuState + * struct via cpu->A / cpu->X / etc. Memory access goes through the + * cpu_read{8,16} / cpu_write{8,16} helpers in cpu_state.h. + */ + +#include +#include + +#include "cpu_state.h" +#include "cpu_trace.h" +#include "common_cpu_infra.h" +#include "funcs.h" + + +/* Forward declarations for in-bank entries. */ +RecompReturn I_IRQ_M0X0(CpuState *cpu); +RecompReturn I_IRQ_M0X1(CpuState *cpu); +RecompReturn I_IRQ_M1X0(CpuState *cpu); +RecompReturn I_IRQ_M1X1(CpuState *cpu); +RecompReturn I_IRQ_M1X1(CpuState *cpu); +RecompReturn I_IRQ_M0X0(CpuState *cpu); +RecompReturn I_IRQ_M0X1(CpuState *cpu); +RecompReturn I_IRQ_M1X0(CpuState *cpu); + +RecompReturn I_IRQ_M1X1(CpuState *cpu) { + extern const char *g_last_recomp_func; + g_last_recomp_func = "I_IRQ_M1X1"; + RecompStackPush("I_IRQ_M1X1"); + cpu_dbg_funcname("I_IRQ_M1X1"); + cpu_trace_func_entry(cpu, 0x0082D8, "I_IRQ_M1X1"); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + if (interp_bridge_in_lle_scheduler()) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + RecompReturn _pending_skip = RECOMP_RETURN_NORMAL; + (void)_pending_skip; /* unused if no NLR site in this fn */ + uint16 _entry_s = cpu->S; + uint8 _hrv = cpu->host_return_valid; + if (cpu_take_tailcall_return_context(&_entry_s, &_hrv)) { + cpu->host_return_valid = _hrv; + } + uint32 _host_return_pc24 = 0xFFFFFFFFu; + if (_hrv == 2 || _hrv == 3) { + uint16 _host_rpcl = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 1u)); + uint16 _host_rpch = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 2u)); + uint8 _host_rpb = (_hrv == 3) ? cpu_read8(cpu, 0x00, (uint16)(_entry_s + 3u)) : cpu->PB; + _host_return_pc24 = ((uint32)_host_rpb << 16) | + (uint16)((((_host_rpch << 8) | _host_rpcl) + 1u) & 0xFFFFu); + } + (void)_entry_s; /* used by trampoline balance check */ + (void)_hrv; + (void)_host_return_pc24; + if (g_recomp_stack_top >= 1) g_cpu_entry_s[g_recomp_stack_top - 1] = _entry_s; + L_82D8_M1X1: + cpu_trace_block(cpu, 0x0082D8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 40; + cpu->master_cycles += 40 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + cpu->_flag_I = 1; + cpu->P = (uint8)(cpu->P | 0x04); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->A); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHA, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->X); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHX, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->Y); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHY, _old_s, -2); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->D); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHD, _old_s, -2); + } + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->DB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHB, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHB, cpu->DB, cpu->DB); + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->PB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHK, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHK, cpu->PB, cpu->PB); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x0082e1u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P | 0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 1 /*SEP*/, _old_p, cpu->P); + } + uint8 _v1 = cpu_read8(cpu, cpu->DB, (uint16)(0x012a)); + cpu_write_a_m(cpu, (uint16)(_v1)); + cpu->_flag_Z = (((_v1 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v1 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_831F_M1X1; } + goto L_82E9_M1X1; /* fall-through */ + L_82E9_M1X1: + cpu_trace_block(cpu, 0x0082E9); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82e9u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v2 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v2)); + cpu->_flag_Z = (((_v2 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v2 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82EE_M1X1; /* fall-through */ + L_82EE_M1X1: + cpu_trace_block(cpu, 0x0082EE); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82eeu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v3 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v3)); + cpu->_flag_Z = (((_v3 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v3 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 1) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82F3_M1X1; /* fall-through */ + L_82F3_M1X1: + cpu_trace_block(cpu, 0x0082F3); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f3u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v4 = cpu_read8(cpu, cpu->DB, (uint16)(0x4212)); + { + uint8 _bt = (uint8)((cpu->A & 0xFF) & (_v4 & 0xFF)); + cpu->_flag_Z = (_bt == 0) ? 1 : 0; + cpu->_flag_N = (((_v4 & 0xFF) & 0x80) != 0) ? 1 : 0; + cpu->_flag_V = (((_v4 & 0xFF) & 0x40) != 0) ? 1 : 0; + } + if (cpu->_flag_V == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_82F3_M1X1; } + goto L_82F8_M1X1; /* fall-through */ + L_82F8_M1X1: + cpu_trace_block(cpu, 0x0082F8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 30; + cpu->master_cycles += 30 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v5 = cpu_read8(cpu, cpu->DB, (uint16)(0x0630)); + cpu_write_a_m(cpu, (uint16)(_v5)); + cpu->_flag_Z = (((_v5 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v5 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v6 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v6); + uint8 _v7 = cpu_read8(cpu, cpu->DB, (uint16)(0x0631)); + cpu_write_a_m(cpu, (uint16)(_v7)); + cpu->_flag_Z = (((_v7 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v7 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v8 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v8); + uint8 _v9 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v9); + uint8 _v10 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v10); + uint8 _v11 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v11)); + cpu->_flag_Z = (((_v11 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v11 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_830F_M1X1; /* fall-through */ + L_830F_M1X1: + cpu_trace_block(cpu, 0x00830F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x830fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 10; + cpu->master_cycles += 10 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v12 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x0128), _v12); + uint8 _v13 = 0x81; + cpu_write_a_m(cpu, (uint16)(_v13)); + cpu->_flag_Z = (((_v13 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v13 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v14 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x4200), _v14); + goto L_8317_M1X1; /* implicit fall-through */ + L_8317_M1X1: + cpu_trace_block(cpu, 0x008317); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x8317u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 34; + cpu->master_cycles += 34 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x008319u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + L_831F_M1X1: + cpu_trace_block(cpu, 0x00831F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x831fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 54; + cpu->master_cycles += 54 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v15 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v15)); + cpu->_flag_Z = (((_v15 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v15 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + cpu->A = (uint16)(cpu->S); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->x_flag) { + uint8 _v = (uint8)(cpu->A & 0xFF); + cpu->X = (uint16)((_v) & 0xFF); /* x=1 zeros high byte (hw contract) */ + cpu->_flag_Z = ((_v) == 0) ? 1 : 0; + cpu->_flag_N = (((_v) & 0x80) != 0) ? 1 : 0; + } else { + cpu->X = (uint16)(cpu->A); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + } + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v16 = cpu_read16(cpu, cpu->DB, (uint16)(0x1f0a)); + cpu_write_a_m(cpu, (uint16)(_v16)); + cpu->_flag_Z = (((_v16 & 0xFFFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v16 & 0xFFFF)) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { uint16 _old_s = cpu->S; + cpu->S = cpu->A; + /* trace_event uses extra0/extra1 for old/new S high bytes */ + cpu_trace_event(cpu, 0, CPU_TR_DB_WRITE, + (uint8)(_old_s >> 8), cpu->S); } + uint16 _v17 = cpu_read_x16(cpu); + cpu_write16(cpu, cpu->DB, (uint16)(0x1f0a), _v17); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x00832du, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + RecompStackPop(); + return RECOMP_RETURN_NORMAL; +} + + +RecompReturn I_IRQ_M0X0(CpuState *cpu) { + extern const char *g_last_recomp_func; + g_last_recomp_func = "I_IRQ_M0X0"; + RecompStackPush("I_IRQ_M0X0"); + cpu_dbg_funcname("I_IRQ_M0X0"); + cpu_trace_func_entry(cpu, 0x0082D8, "I_IRQ_M0X0"); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + if (interp_bridge_in_lle_scheduler()) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + RecompReturn _pending_skip = RECOMP_RETURN_NORMAL; + (void)_pending_skip; /* unused if no NLR site in this fn */ + uint16 _entry_s = cpu->S; + uint8 _hrv = cpu->host_return_valid; + if (cpu_take_tailcall_return_context(&_entry_s, &_hrv)) { + cpu->host_return_valid = _hrv; + } + uint32 _host_return_pc24 = 0xFFFFFFFFu; + if (_hrv == 2 || _hrv == 3) { + uint16 _host_rpcl = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 1u)); + uint16 _host_rpch = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 2u)); + uint8 _host_rpb = (_hrv == 3) ? cpu_read8(cpu, 0x00, (uint16)(_entry_s + 3u)) : cpu->PB; + _host_return_pc24 = ((uint32)_host_rpb << 16) | + (uint16)((((_host_rpch << 8) | _host_rpcl) + 1u) & 0xFFFFu); + } + (void)_entry_s; /* used by trampoline balance check */ + (void)_hrv; + (void)_host_return_pc24; + if (g_recomp_stack_top >= 1) g_cpu_entry_s[g_recomp_stack_top - 1] = _entry_s; + L_82D8_M0X0: + cpu_trace_block(cpu, 0x0082D8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 40; + cpu->master_cycles += 40 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + cpu->_flag_I = 1; + cpu->P = (uint8)(cpu->P | 0x04); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->A); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHA, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->X); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHX, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->Y); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHY, _old_s, -2); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->D); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHD, _old_s, -2); + } + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->DB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHB, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHB, cpu->DB, cpu->DB); + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->PB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHK, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHK, cpu->PB, cpu->PB); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x0082e1u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P | 0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 1 /*SEP*/, _old_p, cpu->P); + } + uint8 _v1 = cpu_read8(cpu, cpu->DB, (uint16)(0x012a)); + cpu_write_a_m(cpu, (uint16)(_v1)); + cpu->_flag_Z = (((_v1 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v1 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_831F_M1X1; } + goto L_82E9_M1X1; /* fall-through */ + L_82E9_M1X1: + cpu_trace_block(cpu, 0x0082E9); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82e9u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v2 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v2)); + cpu->_flag_Z = (((_v2 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v2 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82EE_M1X1; /* fall-through */ + L_82EE_M1X1: + cpu_trace_block(cpu, 0x0082EE); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82eeu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v3 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v3)); + cpu->_flag_Z = (((_v3 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v3 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 1) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82F3_M1X1; /* fall-through */ + L_82F3_M1X1: + cpu_trace_block(cpu, 0x0082F3); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f3u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v4 = cpu_read8(cpu, cpu->DB, (uint16)(0x4212)); + { + uint8 _bt = (uint8)((cpu->A & 0xFF) & (_v4 & 0xFF)); + cpu->_flag_Z = (_bt == 0) ? 1 : 0; + cpu->_flag_N = (((_v4 & 0xFF) & 0x80) != 0) ? 1 : 0; + cpu->_flag_V = (((_v4 & 0xFF) & 0x40) != 0) ? 1 : 0; + } + if (cpu->_flag_V == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_82F3_M1X1; } + goto L_82F8_M1X1; /* fall-through */ + L_82F8_M1X1: + cpu_trace_block(cpu, 0x0082F8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 30; + cpu->master_cycles += 30 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v5 = cpu_read8(cpu, cpu->DB, (uint16)(0x0630)); + cpu_write_a_m(cpu, (uint16)(_v5)); + cpu->_flag_Z = (((_v5 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v5 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v6 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v6); + uint8 _v7 = cpu_read8(cpu, cpu->DB, (uint16)(0x0631)); + cpu_write_a_m(cpu, (uint16)(_v7)); + cpu->_flag_Z = (((_v7 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v7 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v8 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v8); + uint8 _v9 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v9); + uint8 _v10 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v10); + uint8 _v11 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v11)); + cpu->_flag_Z = (((_v11 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v11 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_830F_M1X1; /* fall-through */ + L_830F_M1X1: + cpu_trace_block(cpu, 0x00830F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x830fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 10; + cpu->master_cycles += 10 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v12 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x0128), _v12); + uint8 _v13 = 0x81; + cpu_write_a_m(cpu, (uint16)(_v13)); + cpu->_flag_Z = (((_v13 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v13 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v14 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x4200), _v14); + goto L_8317_M1X1; /* implicit fall-through */ + L_8317_M1X1: + cpu_trace_block(cpu, 0x008317); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x8317u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 34; + cpu->master_cycles += 34 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x008319u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + L_831F_M1X1: + cpu_trace_block(cpu, 0x00831F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x831fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 54; + cpu->master_cycles += 54 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v15 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v15)); + cpu->_flag_Z = (((_v15 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v15 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + cpu->A = (uint16)(cpu->S); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->x_flag) { + uint8 _v = (uint8)(cpu->A & 0xFF); + cpu->X = (uint16)((_v) & 0xFF); /* x=1 zeros high byte (hw contract) */ + cpu->_flag_Z = ((_v) == 0) ? 1 : 0; + cpu->_flag_N = (((_v) & 0x80) != 0) ? 1 : 0; + } else { + cpu->X = (uint16)(cpu->A); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + } + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v16 = cpu_read16(cpu, cpu->DB, (uint16)(0x1f0a)); + cpu_write_a_m(cpu, (uint16)(_v16)); + cpu->_flag_Z = (((_v16 & 0xFFFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v16 & 0xFFFF)) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { uint16 _old_s = cpu->S; + cpu->S = cpu->A; + /* trace_event uses extra0/extra1 for old/new S high bytes */ + cpu_trace_event(cpu, 0, CPU_TR_DB_WRITE, + (uint8)(_old_s >> 8), cpu->S); } + uint16 _v17 = cpu_read_x16(cpu); + cpu_write16(cpu, cpu->DB, (uint16)(0x1f0a), _v17); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x00832du, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + RecompStackPop(); + return RECOMP_RETURN_NORMAL; +} + + +RecompReturn I_IRQ_M0X1(CpuState *cpu) { + extern const char *g_last_recomp_func; + g_last_recomp_func = "I_IRQ_M0X1"; + RecompStackPush("I_IRQ_M0X1"); + cpu_dbg_funcname("I_IRQ_M0X1"); + cpu_trace_func_entry(cpu, 0x0082D8, "I_IRQ_M0X1"); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + if (interp_bridge_in_lle_scheduler()) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + RecompReturn _pending_skip = RECOMP_RETURN_NORMAL; + (void)_pending_skip; /* unused if no NLR site in this fn */ + uint16 _entry_s = cpu->S; + uint8 _hrv = cpu->host_return_valid; + if (cpu_take_tailcall_return_context(&_entry_s, &_hrv)) { + cpu->host_return_valid = _hrv; + } + uint32 _host_return_pc24 = 0xFFFFFFFFu; + if (_hrv == 2 || _hrv == 3) { + uint16 _host_rpcl = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 1u)); + uint16 _host_rpch = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 2u)); + uint8 _host_rpb = (_hrv == 3) ? cpu_read8(cpu, 0x00, (uint16)(_entry_s + 3u)) : cpu->PB; + _host_return_pc24 = ((uint32)_host_rpb << 16) | + (uint16)((((_host_rpch << 8) | _host_rpcl) + 1u) & 0xFFFFu); + } + (void)_entry_s; /* used by trampoline balance check */ + (void)_hrv; + (void)_host_return_pc24; + if (g_recomp_stack_top >= 1) g_cpu_entry_s[g_recomp_stack_top - 1] = _entry_s; + L_82D8_M0X1: + cpu_trace_block(cpu, 0x0082D8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 40; + cpu->master_cycles += 40 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + cpu->_flag_I = 1; + cpu->P = (uint8)(cpu->P | 0x04); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->A); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHA, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->X); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHX, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->Y); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHY, _old_s, -2); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->D); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHD, _old_s, -2); + } + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->DB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHB, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHB, cpu->DB, cpu->DB); + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->PB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHK, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHK, cpu->PB, cpu->PB); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x0082e1u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P | 0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 1 /*SEP*/, _old_p, cpu->P); + } + uint8 _v1 = cpu_read8(cpu, cpu->DB, (uint16)(0x012a)); + cpu_write_a_m(cpu, (uint16)(_v1)); + cpu->_flag_Z = (((_v1 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v1 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_831F_M1X1; } + goto L_82E9_M1X1; /* fall-through */ + L_82E9_M1X1: + cpu_trace_block(cpu, 0x0082E9); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82e9u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v2 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v2)); + cpu->_flag_Z = (((_v2 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v2 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82EE_M1X1; /* fall-through */ + L_82EE_M1X1: + cpu_trace_block(cpu, 0x0082EE); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82eeu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v3 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v3)); + cpu->_flag_Z = (((_v3 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v3 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 1) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82F3_M1X1; /* fall-through */ + L_82F3_M1X1: + cpu_trace_block(cpu, 0x0082F3); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f3u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v4 = cpu_read8(cpu, cpu->DB, (uint16)(0x4212)); + { + uint8 _bt = (uint8)((cpu->A & 0xFF) & (_v4 & 0xFF)); + cpu->_flag_Z = (_bt == 0) ? 1 : 0; + cpu->_flag_N = (((_v4 & 0xFF) & 0x80) != 0) ? 1 : 0; + cpu->_flag_V = (((_v4 & 0xFF) & 0x40) != 0) ? 1 : 0; + } + if (cpu->_flag_V == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_82F3_M1X1; } + goto L_82F8_M1X1; /* fall-through */ + L_82F8_M1X1: + cpu_trace_block(cpu, 0x0082F8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 30; + cpu->master_cycles += 30 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v5 = cpu_read8(cpu, cpu->DB, (uint16)(0x0630)); + cpu_write_a_m(cpu, (uint16)(_v5)); + cpu->_flag_Z = (((_v5 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v5 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v6 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v6); + uint8 _v7 = cpu_read8(cpu, cpu->DB, (uint16)(0x0631)); + cpu_write_a_m(cpu, (uint16)(_v7)); + cpu->_flag_Z = (((_v7 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v7 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v8 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v8); + uint8 _v9 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v9); + uint8 _v10 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v10); + uint8 _v11 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v11)); + cpu->_flag_Z = (((_v11 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v11 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_830F_M1X1; /* fall-through */ + L_830F_M1X1: + cpu_trace_block(cpu, 0x00830F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x830fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 10; + cpu->master_cycles += 10 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v12 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x0128), _v12); + uint8 _v13 = 0x81; + cpu_write_a_m(cpu, (uint16)(_v13)); + cpu->_flag_Z = (((_v13 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v13 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v14 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x4200), _v14); + goto L_8317_M1X1; /* implicit fall-through */ + L_8317_M1X1: + cpu_trace_block(cpu, 0x008317); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x8317u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 34; + cpu->master_cycles += 34 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x008319u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + L_831F_M1X1: + cpu_trace_block(cpu, 0x00831F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x831fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 54; + cpu->master_cycles += 54 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v15 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v15)); + cpu->_flag_Z = (((_v15 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v15 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + cpu->A = (uint16)(cpu->S); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->x_flag) { + uint8 _v = (uint8)(cpu->A & 0xFF); + cpu->X = (uint16)((_v) & 0xFF); /* x=1 zeros high byte (hw contract) */ + cpu->_flag_Z = ((_v) == 0) ? 1 : 0; + cpu->_flag_N = (((_v) & 0x80) != 0) ? 1 : 0; + } else { + cpu->X = (uint16)(cpu->A); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + } + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v16 = cpu_read16(cpu, cpu->DB, (uint16)(0x1f0a)); + cpu_write_a_m(cpu, (uint16)(_v16)); + cpu->_flag_Z = (((_v16 & 0xFFFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v16 & 0xFFFF)) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { uint16 _old_s = cpu->S; + cpu->S = cpu->A; + /* trace_event uses extra0/extra1 for old/new S high bytes */ + cpu_trace_event(cpu, 0, CPU_TR_DB_WRITE, + (uint8)(_old_s >> 8), cpu->S); } + uint16 _v17 = cpu_read_x16(cpu); + cpu_write16(cpu, cpu->DB, (uint16)(0x1f0a), _v17); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x00832du, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + RecompStackPop(); + return RECOMP_RETURN_NORMAL; +} + + +RecompReturn I_IRQ_M1X0(CpuState *cpu) { + extern const char *g_last_recomp_func; + g_last_recomp_func = "I_IRQ_M1X0"; + RecompStackPush("I_IRQ_M1X0"); + cpu_dbg_funcname("I_IRQ_M1X0"); + cpu_trace_func_entry(cpu, 0x0082D8, "I_IRQ_M1X0"); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + if (interp_bridge_in_lle_scheduler()) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + RecompReturn _pending_skip = RECOMP_RETURN_NORMAL; + (void)_pending_skip; /* unused if no NLR site in this fn */ + uint16 _entry_s = cpu->S; + uint8 _hrv = cpu->host_return_valid; + if (cpu_take_tailcall_return_context(&_entry_s, &_hrv)) { + cpu->host_return_valid = _hrv; + } + uint32 _host_return_pc24 = 0xFFFFFFFFu; + if (_hrv == 2 || _hrv == 3) { + uint16 _host_rpcl = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 1u)); + uint16 _host_rpch = cpu_read8(cpu, 0x00, (uint16)(_entry_s + 2u)); + uint8 _host_rpb = (_hrv == 3) ? cpu_read8(cpu, 0x00, (uint16)(_entry_s + 3u)) : cpu->PB; + _host_return_pc24 = ((uint32)_host_rpb << 16) | + (uint16)((((_host_rpch << 8) | _host_rpcl) + 1u) & 0xFFFFu); + } + (void)_entry_s; /* used by trampoline balance check */ + (void)_hrv; + (void)_host_return_pc24; + if (g_recomp_stack_top >= 1) g_cpu_entry_s[g_recomp_stack_top - 1] = _entry_s; + L_82D8_M1X0: + cpu_trace_block(cpu, 0x0082D8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82d8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 40; + cpu->master_cycles += 40 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + cpu->_flag_I = 1; + cpu->P = (uint8)(cpu->P | 0x04); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->A); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHA, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->X); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHX, _old_s, -2); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->Y); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHY, _old_s, -2); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S - 1); + cpu_write16(cpu, 0x00, cpu->S, cpu->D); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHD, _old_s, -2); + } + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->DB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHB, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHB, cpu->DB, cpu->DB); + { + uint16 _old_s = cpu->S; + cpu_write8(cpu, 0x00, cpu->S, (uint8)(cpu->PB)); + cpu->S = (uint16)(cpu->S - 1); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PHK, _old_s, -1); + } + cpu_trace_event(cpu, 0, CPU_TR_PHK, cpu->PB, cpu->PB); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x0082e1u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P | 0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 1 /*SEP*/, _old_p, cpu->P); + } + uint8 _v1 = cpu_read8(cpu, cpu->DB, (uint16)(0x012a)); + cpu_write_a_m(cpu, (uint16)(_v1)); + cpu->_flag_Z = (((_v1 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v1 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_831F_M1X1; } + goto L_82E9_M1X1; /* fall-through */ + L_82E9_M1X1: + cpu_trace_block(cpu, 0x0082E9); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82e9u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v2 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v2)); + cpu->_flag_Z = (((_v2 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v2 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82EE_M1X1; /* fall-through */ + L_82EE_M1X1: + cpu_trace_block(cpu, 0x0082EE); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82eeu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v3 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v3)); + cpu->_flag_Z = (((_v3 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v3 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_Z == 1) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_82F3_M1X1; /* fall-through */ + L_82F3_M1X1: + cpu_trace_block(cpu, 0x0082F3); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f3u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 6; + cpu->master_cycles += 6 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v4 = cpu_read8(cpu, cpu->DB, (uint16)(0x4212)); + { + uint8 _bt = (uint8)((cpu->A & 0xFF) & (_v4 & 0xFF)); + cpu->_flag_Z = (_bt == 0) ? 1 : 0; + cpu->_flag_N = (((_v4 & 0xFF) & 0x80) != 0) ? 1 : 0; + cpu->_flag_V = (((_v4 & 0xFF) & 0x40) != 0) ? 1 : 0; + } + if (cpu->_flag_V == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_82F3_M1X1; } + goto L_82F8_M1X1; /* fall-through */ + L_82F8_M1X1: + cpu_trace_block(cpu, 0x0082F8); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x82f8u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 30; + cpu->master_cycles += 30 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v5 = cpu_read8(cpu, cpu->DB, (uint16)(0x0630)); + cpu_write_a_m(cpu, (uint16)(_v5)); + cpu->_flag_Z = (((_v5 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v5 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v6 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v6); + uint8 _v7 = cpu_read8(cpu, cpu->DB, (uint16)(0x0631)); + cpu_write_a_m(cpu, (uint16)(_v7)); + cpu->_flag_Z = (((_v7 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v7 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v8 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x2111), _v8); + uint8 _v9 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v9); + uint8 _v10 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x2112), _v10); + uint8 _v11 = cpu_read8(cpu, cpu->DB, (uint16)(0x0128)); + cpu_write_a_m(cpu, (uint16)(_v11)); + cpu->_flag_Z = (((_v11 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v11 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->_flag_N == 0) { cpu->cycles += 1; cpu->master_cycles += ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); goto L_8317_M1X1; } + goto L_830F_M1X1; /* fall-through */ + L_830F_M1X1: + cpu_trace_block(cpu, 0x00830F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x830fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 10; + cpu->master_cycles += 10 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v12 = 0x0; + cpu_write8(cpu, cpu->DB, (uint16)(0x0128), _v12); + uint8 _v13 = 0x81; + cpu_write_a_m(cpu, (uint16)(_v13)); + cpu->_flag_Z = (((_v13 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v13 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v14 = cpu_read_a16(cpu); + cpu_write8(cpu, cpu->DB, (uint16)(0x4200), _v14); + goto L_8317_M1X1; /* implicit fall-through */ + L_8317_M1X1: + cpu_trace_block(cpu, 0x008317); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x8317u)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 34; + cpu->master_cycles += 34 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x008319u, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + L_831F_M1X1: + cpu_trace_block(cpu, 0x00831F); + WatchdogCheck(); + if (interp_bridge_lle_master_deadline_reached(cpu)) { + RecompStackPopYield(); + return interp_bridge_lle_yield_unwind(cpu, (((uint32)cpu->PB << 16) | 0x831fu)); + } + cpu->coprocessor_master_cycles = cpu->master_cycles; + cpu->cycles += 54; + cpu->master_cycles += 54 * ((g_memsel && (cpu->PB & 0x80)) ? 6 : 8); + uint8 _v15 = cpu_read8(cpu, cpu->DB, (uint16)(0x4211)); + cpu_write_a_m(cpu, (uint16)(_v15)); + cpu->_flag_Z = (((_v15 & 0xFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v15 & 0xFF)) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { + uint8 _old_p = cpu->P; + cpu_mirrors_to_p(cpu); + cpu->P = (uint8)(cpu->P & ~0x30); + cpu_p_to_mirrors(cpu); + cpu_trace_px_record(cpu, 0, 0 /*REP*/, _old_p, cpu->P); + } + cpu->A = (uint16)(cpu->S); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + if (cpu->x_flag) { + uint8 _v = (uint8)(cpu->A & 0xFF); + cpu->X = (uint16)((_v) & 0xFF); /* x=1 zeros high byte (hw contract) */ + cpu->_flag_Z = ((_v) == 0) ? 1 : 0; + cpu->_flag_N = (((_v) & 0x80) != 0) ? 1 : 0; + } else { + cpu->X = (uint16)(cpu->A); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + } + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + uint16 _v16 = cpu_read16(cpu, cpu->DB, (uint16)(0x1f0a)); + cpu_write_a_m(cpu, (uint16)(_v16)); + cpu->_flag_Z = (((_v16 & 0xFFFF)) == 0) ? 1 : 0; + cpu->_flag_N = ((((_v16 & 0xFFFF)) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + { uint16 _old_s = cpu->S; + cpu->S = cpu->A; + /* trace_event uses extra0/extra1 for old/new S high bytes */ + cpu_trace_event(cpu, 0, CPU_TR_DB_WRITE, + (uint8)(_old_s >> 8), cpu->S); } + uint16 _v17 = cpu_read_x16(cpu); + cpu_write16(cpu, cpu->DB, (uint16)(0x1f0a), _v17); + { uint8 _old_db = cpu->DB; uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->DB = cpu_read8(cpu, 0x00, cpu->S); + cpu->_flag_Z = ((cpu->DB) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->DB) & 0x80) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLB, _old_s, +1); + cpu_trace_db_change(cpu, 0x00832du, _old_db, cpu->DB, CPU_TR_PLB); } + { + uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->D = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->D) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->D) & 0x8000) != 0) ? 1 : 0; + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLD, _old_s, 2); + } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->Y = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->Y) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->Y) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLY, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->X = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->X) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->X) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLX, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + { uint16 _old_s = cpu->S; + cpu->S = (uint16)(cpu->S + 1); + cpu->A = cpu_read16(cpu, 0x00, cpu->S); + cpu->S = (uint16)(cpu->S + 1); + cpu->_flag_Z = ((cpu->A) == 0) ? 1 : 0; + cpu->_flag_N = (((cpu->A) & 0x8000) != 0) ? 1 : 0; + cpu_trace_stack_op(cpu, 0, CPU_STACK_OP_PLA, _old_s, +2); + cpu->P = (uint8)((cpu->P & ~0x82) | (cpu->_flag_Z ? 0x02 : 0) | (cpu->_flag_N ? 0x80 : 0)); } + cpu_trace_event(cpu, 0, CPU_TR_RTI, 0, 0); + { cpu->S = (uint16)(cpu->S + 1); cpu->P = cpu_read8(cpu, 0x00, cpu->S); cpu_p_to_mirrors(cpu); + cpu->S = (uint16)(cpu->S + 2); /* pull + discard PC */ + if (!cpu->emulation) cpu->S = (uint16)(cpu->S + 1); /* native: pull + discard PB */ + cpu_trace_px_record(cpu, 0, 3 /*RTI*/, cpu->P, cpu->P); + RecompStackPop(); + return RECOMP_RETURN_NORMAL; /* RTI: popped interrupt frame */ } + RecompStackPop(); + return RECOMP_RETURN_NORMAL; +} + + +void I_IRQ(CpuState *cpu) { + RecompReturn _r; + switch (((cpu->m_flag & 1) << 1) | (cpu->x_flag & 1)) { + case 0: _r = I_IRQ_M0X0(cpu); break; + case 1: _r = I_IRQ_M0X1(cpu); break; + case 2: _r = I_IRQ_M1X0(cpu); break; + case 3: _r = I_IRQ_M1X1(cpu); break; + default: _r = interp_tier_dispatch(cpu, 0x0082d8u); break; + } + if (_r != RECOMP_RETURN_NORMAL) { + fprintf(stderr, + "[recomp] non-local-return SKIP_%d leaked past void alias %s\n", + (int)_r, "I_IRQ"); + abort(); + } +} diff --git a/src/gen/dispatch_v2.c b/src/gen/dispatch_v2.c new file mode 100644 index 0000000..f1e5a13 --- /dev/null +++ b/src/gen/dispatch_v2.c @@ -0,0 +1,21 @@ +/* Auto-generated from the authoritative LLE/AOT manifest. */ +#include "cpu_state.h" + +RecompReturn I_IRQ_M0X0(CpuState *cpu); +RecompReturn I_IRQ_M0X1(CpuState *cpu); +RecompReturn I_IRQ_M1X0(CpuState *cpu); +RecompReturn I_IRQ_M1X1(CpuState *cpu); + +const DispatchEntry g_dispatch_table[] = { + { 0x0082D8u, { I_IRQ_M0X0, I_IRQ_M0X1, I_IRQ_M1X0, I_IRQ_M1X1 }, 0 }, /* I_IRQ */ +}; + +const unsigned g_dispatch_table_count = + (unsigned)(sizeof(g_dispatch_table) / sizeof(g_dispatch_table[0])); + +const RamRoutineGuard g_ram_routine_guards[] = { + { 0xFFFFFFFFu, 0u, 0u }, +}; + +const unsigned g_ram_routine_guard_count = + (unsigned)(sizeof(g_ram_routine_guards) / sizeof(g_ram_routine_guards[0])); diff --git a/src/gen/module_v2.c b/src/gen/module_v2.c new file mode 100644 index 0000000..4f9e079 --- /dev/null +++ b/src/gen/module_v2.c @@ -0,0 +1,39 @@ +/* Auto-generated by snesrecomp v2 program_emit. Do NOT hand-edit. + * + * Program module `main`. + * Registers this generated tree's dispatch/guard tables with the + * runtime module registry (runner/src/program_module.h) so a host + * can select it by id. */ +#include + +#include "cpu_state.h" +#include "program_module.h" + +extern const DispatchEntry g_dispatch_table[]; +extern const unsigned g_dispatch_table_count; +extern const RamRoutineGuard g_ram_routine_guards[]; +extern const unsigned g_ram_routine_guard_count; + +SnesProgramModule g_program_module; + +SNES_PROGRAM_MODULE_CONSTRUCTOR(snes_program_module_register_generated) { + g_program_module.id = "main"; + g_program_module.symbol_prefix = ""; + g_program_module.program_digest = "613ba97f57adfef1b31a722cde80b1f40f6c8a74b5b5a6d21611b09b953083c6"; + g_program_module.build_digest = "b7cae10b1c212cb9fd725d1ddfa3c61092a2ff25d71a96363c8a71bd72df64f8"; + g_program_module.dispatch = g_dispatch_table; + g_program_module.dispatch_count = g_dispatch_table_count; + g_program_module.guards = g_ram_routine_guards; + g_program_module.guard_count = g_ram_routine_guard_count; + g_program_module.rom_size = 1048576u; + { + static const uint8_t digest[32] = { + 0x66, 0x87, 0x1d, 0x66, 0xbe, 0x19, 0xad, 0x2c, + 0x34, 0xc9, 0x27, 0xd6, 0xb1, 0x4c, 0xd8, 0xeb, + 0x6f, 0xc3, 0x18, 0x19, 0x65, 0xb6, 0xe5, 0x17, + 0xcb, 0x36, 0x1f, 0x73, 0x16, 0x00, 0x9c, 0xfb, + }; + memcpy(g_program_module.rom_sha256, digest, sizeof(digest)); + } + snes_program_module_register(&g_program_module); +} diff --git a/src/gen/program_manifest.json b/src/gen/program_manifest.json new file mode 100644 index 0000000..c40bf90 --- /dev/null +++ b/src/gen/program_manifest.json @@ -0,0 +1,85 @@ +{ + "exit_mode_sets": {}, + "exit_modes": {}, + "format_version": 3, + "nodes": { + "0082D8:M0X0": { + "demands": [], + "digest": "native", + "disposition": "aot_eligible", + "instruction_count": 49, + "key": { + "m": 0, + "pc24": 33496, + "x": 0 + }, + "max_pc24": 33586, + "min_pc24": 33496, + "reasons": [] + }, + "0082D8:M0X1": { + "demands": [], + "digest": "native", + "disposition": "aot_eligible", + "instruction_count": 49, + "key": { + "m": 0, + "pc24": 33496, + "x": 1 + }, + "max_pc24": 33586, + "min_pc24": 33496, + "reasons": [] + }, + "0082D8:M1X0": { + "demands": [], + "digest": "native", + "disposition": "aot_eligible", + "instruction_count": 49, + "key": { + "m": 1, + "pc24": 33496, + "x": 0 + }, + "max_pc24": 33586, + "min_pc24": 33496, + "reasons": [] + }, + "0082D8:M1X1": { + "demands": [], + "digest": "native", + "disposition": "aot_eligible", + "instruction_count": 49, + "key": { + "m": 1, + "pc24": 33496, + "x": 1 + }, + "max_pc24": 33586, + "min_pc24": 33496, + "reasons": [] + } + }, + "roots": [ + { + "m": 0, + "pc24": 33496, + "x": 0 + }, + { + "m": 0, + "pc24": 33496, + "x": 1 + }, + { + "m": 1, + "pc24": 33496, + "x": 0 + }, + { + "m": 1, + "pc24": 33496, + "x": 1 + } + ] +} diff --git a/src/gen/unresolved_stubs_v2.c b/src/gen/unresolved_stubs_v2.c new file mode 100644 index 0000000..7850fd2 --- /dev/null +++ b/src/gen/unresolved_stubs_v2.c @@ -0,0 +1 @@ +/* Manifest-driven generation: unresolved execution remains LLE. */